With constant evolution of manufacturing processes and equipment tools, various types and/or shapes of structures of semiconductor devices have been developed so far with constant improving performance and/or specialized functionalities. Taking semiconductor transistors as an example, there are regular planar-type field-effect-transistors (FETs) as well as recently developed fin-type field-effect-transistors (finFETs). Furthermore, among finFETs, there are silicon-on-insulator (SOI) based finFETs and bulk finFETs. On the other hand, from device functionality standpoint, there are p-type transistors and n-type transistors that are characterized by the type of charge careers that the transistors employ. For example, there are p-type bulk finFETs and n-type bulk finFETs.
It is also known in the art that performance of a transistor generally improves with the right type of strain being present in the channel region of the transistor. For example, compressive strain is in general favorably used in a p-type transistor and tensile strain is in general favorably used in an n-type transistor in order to improve mobility of careers in the channel. In a traditional planar-type FET, as an example, a stress-liner (either compressive or tensile) may be applied to regions of the transistor to achieve the above goal of creating strain in the channel region. However, there has been no effective way of applying stress to a fin-type bulk field-effect-transistor or finFET. In particular, it is known to be a challenging task to apply tensile stress to the channel region of an n-type bulk finFET.